The envisioned ERA platform is adaptive and employs a structured design to integrate the necessary computing, networking, and memory elements. The adaptivity enables the platform to adapt itself to the characteristics and requirements of the applications (current and future) while taking into account performance and power constraints within its operating environment.

ERA aims at investigating and developing new methodologies in both tools and hardware designs to break through current power and memory walls for the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance for given power budgets for a (set of) targeted application(s). This is a departure from utilizing fixed designs that limit their use to their intended application(s) and that require additional design effort to target new applications.

ERA Overview

Technical Approach

In detail, the ERA project focuses on three hardware components (processor core, memory hierarchy, and network-on-chip) in the design of an embedded system platform without losing sight of the requirements posed by the (embedded) applications. The adaptability of the envisioned platform opens up new compilation strategies and scheduling techniques (either in hardware or by an operating system) to deal with this increased freedom. In the following, we summarize the recent developments on the highlighted points of focus (in bold) within the ERA project:

  • We are developing a dynamically reconfigurable parameterized processor core that can adapt itself to the application needs or the power budget at hand through parameters such as issue width, register file size, type and number of functional units, and memory bandwidth. For example, when an application (thread) exhibits a high level of parallelism, more issue slots, a larger register file, and more functional units are instantiated to better execute the application (thread). However, if the power budget does not allow for such an instantiation, the platform will decide to reduce the number of resources to meet the power constraints and provide the right amount of performance. For this purpose, we designed and verified several instances of the ERA platform components on the latest generation FPGA chips.
  • We are investigating a dynamically adjustable memory hierarchy that can be tailored to the application behavior in order to improve the utilization of the available memory bandwidth. Example parameters include: cache size, cache line size, and set associativity. Moreover, in order to avoid cache misses during a transitional phase between configurations, we are currently developing mechanisms that allow for smooth transitions.
  • We are developing a dynamically reconfigurable network-on-chip (NoC) that can adjust itself to the traffic that is "flowing" through its nodes. In more detail, the NoC allocates more resources to the nodes when it determines that certain paths in the network are more frequently taken. Our initial design shows promising results and it is currently being integrated with the earlier mentioned processor cores allowing for further energy reductions.
  • We are investigating the characteristics of (embedded) applications (working on top of an embedded OS) to determine how to best map such characteristics to the parameters we identified in the design of the hardware components. This work is performed by identifying phases within applications that will benefit from different hardware configurations and therefore, require the need for dynamic reconfiguration.
  • We are investigating new compilation techniques to deal with the underlying dynamic behavior of the hardware components in order to better utilize the available resources without losing generality in generating application software.
  • We are extending an embedded OS to work in conjunction with a hardware scheduler to manage the hardware resources and schedule a given set of applications that need to be executed.


Demonstration and Use

In the ERA project, we will deliver the ERA platform incorporating the earlier mentioned components (processor core, memory hierarchy, network-on-chip) and demonstrate how the different components dynamically adapt themselves. Subsequently, we will demonstrate using our own benchmarks (for example, mobile video and other mobile applications taken from the multimedia and mobile computing area) what gains in terms of performance and energy consumption can be obtained and how the trade-offs of the different components interact with each other in terms of performance and energy consumption.

Scientific, Economic, and Societal Impact

The final ERA platform is mainly intended to be published as an open-source platform that both the industry and academia can use for fast design-space exploration and prototyping. More precisely, the academic partners can use the platform to assist in their research into computer architecture and code compilation for adaptive platforms. Furthermore, we envision the platform to be adapted for use in computer architecture and embedded systems courses in leading universities worldwide. Consequently, the project outcome will lead to more knowledgeable and experienced engineers to design future embedded systems, and thereby further extending the leadership of Europe in this area. Overall, we expect that our ERA platform can lead to cheaper embedded system (as no large redesigns are needed for future product generations), faster products (by dynamically adding computing resources), and more power-efficient products (as the hardware tunes itself to provide adequate performance based on limited power budgets).


Within the ERA project, we already have achieved the following:

  • several designs of a parameterized reconfigurable processor (soft)core
  • an ERA platform with the Linux OS driver controlling the instantiation and execution of our parameterized reconfigurable processor core
  • a stand-alone version of our processor core with its own memory hierarchy (both in simulation and in hardware)
  • a set of dynamic adaptive cache algorithms (also implemented in the simulator)
  • a categorization of our ERA benchmark suite
  • a design of a reconfigurable NoC
  • a port of GCC targeting the VEX ISA